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#Synplify pro rom inferencing portable
#Synplify pro rom inferencing code

Altera supports byte-enables on both simple and true dual-port memories. Xilinx only supports byte-enables on single-port memories. Both Xilinx and Altera support inferring byte-enables, to a certain extent.Unfortunately, neither uses constructs that the other can understand. Altera supports this in VHDL and SystemVerilog (but not plain Verilog). Xilinx supports this in VHDL and Verilog. Port A views a memory as 512×36, while Port B views the exact same memory as 1024×18).

Both Xilinx and Altera support inferring dual-port RAMs with mixed-width ports (e.g.

a few interesting differences can be found between Xilinx’s and Altera’s respective abilities to infer memories:

and performing a few non-exhaustive synthesis experiments of my own,.

reviewing each vendor’s language templates: Edit->Language Templates in ISE’s GUI, followed by drilling down to ->Full Designs->RAMs and ROMs.

reviewing each vendor’s pertinent documentation: the “RAMs Hardware Description Language (HDL) Coding Guidelines” from Xilinx’s XST User Guide for Virtex-6 and Spartan-6 Devices (the pre-6 XST guide doesn’t cover any of XST’s more advanced inference capabilities), and the “Inferring Memory Functions from HDL Code” section of Altera’s Recommended HDL Coding Styles.

There are, of course, a variety of limitations and caveats that come along with that statement.

#Synplify pro rom inferencing code

Using current synthesis tools from Xilinx ( ISE WebPack 12.2) and Altera ( Quartus II Web Edition 10.0 SP1), it’s now practical to write synthesizable device and vendor-independent Verilog code (or VHDL, if that’s your thing) that properly infers true dual-port (TDP), dual-clock block RAMs in each vendor’s respective FPGAs. Which is, perhaps, a little bit silly – considering that the whole point behind this little exercise is to be able to write code that isn’t tied to any particular tool, device or vendor! Figuring out exactly the right sort of Verilog to get multiple tools to infer the block you want can be even trickier. Figuring out exactly the right sort of Verilog required to get a particular tool to infer the block you want isn’t always straight-forward. The trick is that little “properly coded” clause.

#Synplify pro rom inferencing portable

Spartan 6 to Cyclone III), and even be portable to vendor-independent environments (e.g. Spartan 3E to Virtex 6), be portable between devices from different vendors (e.g. block RAMs) should: be portable between devices from a particular vendor (e.g. Properly coded, a module that infers technology-dependent blocks (e.g. I’m a big fan of inference, especially as it applies to writing synthesizable Verilog code for FPGAs. Yes, it’s actually possible! – in Verilog and VHDL, even.